The present invention relates to a driving circuit, a charge/discharge circuit and the like for driving a capacitive load, and more particularly, to a driving circuit, a charge/discharge circuit and the like that are suitable for a liquid crystal display device and the like using an active matrix driving method.
In recent years, with development of communication technology, demand has increased for portable equipment with a display that includes a mobile phone, a personal digital assistant and the like. It is important for portable equipment to have sufficiently long continuous use, and a liquid crystal display device has been widely used for a display of portable equipment because of its low power consumption.
Further, although a liquid crystal display device has been conventionally translucent with backlighting, a reflective display, which uses extraneous light without backlighting, has been developed so as to further lower power consumption.
Moreover, as for a liquid crystal display device, a clear image display has been demanded with higher resolution. Thus, demand has increased for a liquid crystal display device using an active matrix driving method that can provide a clearer image than a conventional direct matrix method.
Lower power consumption has been also demanded on a driving circuit of a liquid crystal display device. A driving circuit with low power consumption has been earnestly studied and developed.
In general, as shown in FIG. 1, a liquid crystal display device 1000 using an active matrix driving method includes a liquid crystal driving device 1010 and a liquid crystal panel 1020. Moreover, the liquid crystal driving device 1010 includes a control circuit 1011, a data line driving circuit 1012, and a common electrode voltage generating circuit 1013. The liquid crystal panel 1020 includes a semiconductor substrate (TFT substrate) 1021 having transparent pixel electrodes and a thin-film transistor (TFT) thereon, an opposing substrate 1022 having a transparent common electrode formed entirely thereon, and liquid crystal filled between the two substrates being opposed to each other.
Data lines and scanning lines are disposed on the semiconductor substrate (TFT substrate) 1021. The data lines transmit a plurality of level voltages (gradation voltage) to be applied to the pixel electrodes and the scanning lines transmit switching (scanning) control signals to TFT elements. The data lines have a relatively large capacitive load due to a liquid crystal capacity between the opposing substrate electrodes, a capacity appearing on the intersections with the scanning lines, and the like.
The following will discuss a liquid crystal driving device of the liquid crystal display device.
The control circuit 1011 generates a driving control signal, a scan control signal, a common electrode control signal, and so on in response to a signal such as a parallel synchronizing signal and a video signal.
The data line driving circuit 1012 generates a plurality of gradation voltages for driving the data lines in response to a driving control signal.
Moreover, the common electrode voltage generating circuit 1013 supplies a predetermined voltage to the common electrode in response to a common electrode control signal.
A scan control signal controls the TFT, gradation voltage is applied to the pixel electrodes, a transmittance of liquid crystal is varied according to a potential difference between the pixel electrode and the opposing substrate electrode, and an image is displayed.
Gradation voltage is applied to the pixel electrodes via the data lines and is applied to all the pixels connected to the data lines in a single frame period (about {fraction (1/60)} second). Hence, the data line driving circuit needs to rapidly drive the data lines serving as a capacitive load with high voltage accuracy.
As described above, the data line driving circuit 1012 needs to rapidly drive the data lines serving as a capacitive load with high voltage accuracy. Further, when being used for portable equipment, low power consumption is demanded. Therefore, a variety of data line driving circuits have been developed to satisfy the above-mentioned needs (high accuracy, high speed, and low consumption of output voltage).
As a simple driving circuit for outputting a plurality of level voltages in FIG. 1, a driving circuit of FIG. 2 has been known, which is composed of a resistor string (multilevel voltage generating circuit) 200 and decoders 300 each including a switch group 301.
In FIG. 2, as a simple configuration, voltage taken out from a connecting terminal of the resistor string (multilevel voltage generating circuit) 200 is selected in the decoder 300 including the switch group 301, and the voltage is directly outputted to the data lines of a liquid crystal display panel (e.g., 1020 in FIG. 1) connected to a output terminal group 400. Besides, a level voltage corresponding to each data line can be selected in the decoder 300 in response to a digital select control signal, which is one of driving control signals.
Power consumption of the driving circuit shown in FIG. 2 is determined by current applied to the resistor string 200. If the current is lowered, power consumption can be reduced. However, a driving period (a single output period) of a level voltage to the data line is generally determined by the number of scanning lines of the liquid crystal display panel. In case of a panel having a large number of pixels, a single output period is short and high-speed driving is necessary.
A speed of the driving circuit shown in FIG. 2 is dependent upon the magnitude of current applied to the resistor string 200, and charge supplied to the data lines is supplied from the resistor string 200. Hence, the circuit is large in impedance, and it is necessary to sufficiently increase the current of the resistor string 200 to perform high-speed driving in the driving circuit shown in FIG. 2. In this case, power consumption increases.
As a driving circuit for solving the above problem, for example, Japanese Patent Laid-Open No. 10-301539 discloses a driving circuit configured as FIG. 3.
Referring to FIG. 3, the driving circuit includes output circuits 900, which are respectively disposed on the outputs of the driving circuit shown in FIG. 2. The output circuit 900 has a switch 901 which connects the output of the decoder 300 and an output terminal 400, an N-channel MOS transistor (NMOS) 902, and a P-channel MOS transistor (PMOS) 903. The N-channel MOS transistor (NMOS) 902 has the drain connected to a high-potential side power source VDD, the source connected to the output terminal 400, and the gate connected to the output of the decoder 300. The P-channel MOS transistor (PMOS) 903 has the source connected to the output terminal 400, the drain connected to a lower-potential side power source VSS, and the gate connected to the output of the decoder 300.
Besides, the switch 901 is controlled by, for example, an operating control signal generated in an operating control signal generating circuit 800 or an operating control signal generated in the control circuit 1011 of FIG. 1. Namely, when the switch 901 is turned off during a spare charge/discharge period, which is provided in a first half of an output period, a source follower operation of the transistor 902 or 903 achieves faster speed to about a voltage shifted from a selected level voltage by a threshold voltage of the transistor. After the spare charge/discharge period, the switch 901 is turned on, charge is directly supplied from the resistor string 200 to the data lines like the driving circuit shown in FIG. 2, and driving is made at a selected level voltage.
In the driving circuit of FIG. 3, during the spare charge/discharge period, charge is supplied from the power source, which is connected to the drain of the transistor, to the data lines by impedance conversion in the source follower operation of the transistor. Thus, fast driving is possible.
Therefore, the driving circuit of FIG. 3 can provide driving to a selected level voltage faster than the driving circuit shown in FIG. 2.
Meanwhile, a driving circuit has been known which achieves high-speed driving completely by impedance conversion without supplying charge from the resistor string 200 to the data lines. FIG. 4 shows an example of a representative driving circuit.
Referring to FIG. 4, a driving circuit is composed of an operational amplifier, which is constituted by differential amplifying stages 81 and 82, and an output amplifying stage 84. In FIG. 4, when a voltage following structure is provided in which the output voltage Vout of the operational amplifier is fed back (negative feedback) to the Vinxe2x88x92 (reversed input end) of the differential amplifying stages 81 and 82, a voltage equal to that inputted to the Vin+ (non-inverting input terminal) is amplified in current and is outputted as the output voltage Vout.
Therefore, when a level voltage is inputted to the Vin+, the data lines can be rapidly driven with high current supplying capability.
Regarding an operation of the operational amplifier in FIG. 4 having a voltage following structure, although the output voltage Vout is stable at Vin+=Vinxe2x88x92, when the voltage is changed to Vin+ greater than Vinxe2x88x92, only a PMOS transistor 841 of the output amplifying stage 84 is operated and the output voltage Vout is increased to Vin+ (voltage on a non-inverting input terminal). Meanwhile, when the voltage is changed to Vin+ less than Vinxe2x88x92, only an NMOS transistor 842 of the output amplifying stage 84 is operated, and the output voltage Vout is reduced to Vinxe2x88x92 (voltage on a reversed input end).
In the configuration having feedback, oscillation is likely to occur because of delays in responses of the differential amplifying stages 81 and 82 and the output amplifying stage 84 with respect to a change in output voltage Vout. Hence, capacitor elements 843 and 844 are provided as phase compensating means to adjust delayed timing of response (phase compensation). Thus, it is possible to prevent oscillation and obtain output voltage with stability. Such an operational amplifier makes it possible to drive the data lines with high speed. Additionally, when the operational amplifier of FIG. 4 is used as the output circuit 900 of FIG. 3, small current supplying capability is enough for the circuit supplying Vin+. Hence, it is possible to sufficiently reduce the current of the resistor string 200.
However, in the operational amplifier in FIG. 4, power is consumed due to charge/discharge power of a capacitive load and idling current for maintaining the operation of the operational amplifier. Further, when a level voltage inputted to Vin+ is changed, a charging operation and a discharging operation are switched with high speed until the output voltage is stabilized. Thus, an extremely large power may be consumed in a short time. Hence, although the operational amplifier shown in FIG. 4 can achieve high voltage accuracy and high-speed driving, power consumption is large.
As a driving circuit for solving the above problem, for example, Japanese Patent No. 2990082 discloses a driving circuit shown in FIG. 5. Referring to FIG. 5, the driving circuit is constituted by an operational amplifier, which is composed of a differential amplifying stage 81 and an output amplifying stage 83, and a spare discharge control switch 834.
Although the output amplifying stage 83 can perform a charging operation with high speed by using a PMOS transistor 831, a speed of a discharging operation is reduced by the current of a constant current circuit 832. Hence, a spare discharging period is provided in a first half of an outputting period. Data lines are temporarily reduced to a source voltage VSS during the spare discharging period by the switch 834, which is controlled by an operation control signal, and is driven to the inputted voltage Vin+ with high speed by the operational amplifier after the spare discharging period.
This makes it possible to reduce currents of constant current circuits 815 and 832 of the differential amplifying stage 81 and the output amplifying stage 83 so as to achieve high-speed driving even when idling current is reduced.
Namely, in the driving circuit shown in FIG. 5, the data lines are temporarily predischarged to the power source voltage VSS. Thus, high-speed driving can be achieved by the operational amplifier having low power consumption with small idling current and driving can be provided with high voltage accuracy of the operational amplifier.
Also, without the necessity for precharging, high-speed driving is possible with such a simple operational amplifier as the differential amplifying stage 81 and the output amplifying stage 83 of FIG. 5.
Further, as a driving circuit achieving low power consumption, for example, Japanese Patent Laid-Open No. 10-197848 discloses a configuration shown in FIG. 6.
Referring to FIG. 6, a feedback configuration is provided, in which an operational amplifier 860 having the input voltage Vin inputted to the reversed input end (xe2x88x92), a PMOS transistor 861 having the source connected to the high-potential side power source VDD via a switch 871, and an NMOS transistor 862 having the source connected to a low-potential side power source VSS via a switch 872. The drains of the PMOS transistor 861 and the NMOS transistor 862 are connected in common to the output terminal, the output of the operational amplifier 860 is connected in common to the gates of the PMOS transistor 861 and the NMOS transistor 862, and the voltage Vout of the output terminal is fed back to the non-inverting input terminal (+) of the operational amplifier 860.
The operational amplifier 860 is configured such that only the gates of the transistors 861 and 862 are driven. Hence, even when the operational amplifier 860 has low power consumption with reduced current supply capability, it is possible to drive the gates of the transistors 861 and 862 with high speed. Moreover, the transistors 861 and 862 can rapidly charge or discharge a capacitive load with high current supply capability and are stabilized at a voltage equal to that of the input of the operational amplifier 860.
Therefore, high-speed driving is possible in the driving circuit of FIG. 6. Besides, the switches 871 and 872 are controlled by an operation control signal and are provided for preventing flow-through current caused by the switching of charging and discharging. When the PMOS transistor 861 carries out a charging operation, the switch 871 is turned on. When the NMOS transistor 862 carries out a discharging operation, the switch 872 is turned on. Hence, high-speed driving is achieved and power consumption can be reduced to charge/discharge power of the capacitive load and idling current of the operational amplifier 860.
As described above, regarding the driving circuit of the liquid crystal display device used for portable equipment, low power consumption is required more than anything else. At the same time, high-speed driving with high voltage accuracy is necessary.
The driving circuit shown in FIG. 3 rapidly precharges/predischarges the data lines to a voltage shifted from a selected level voltage by about a threshold voltage of the transistor. And then, charge is directly supplied from the resistor string 200 and provides driving at a selected level voltage. Thus, faster driving is possible than the driving circuit shown in FIG. 2. However, in FIG. 3 as well, as for a change by about a threshold voltage of the transistor, driving needs to be made by directly supplying charge from the resistor string 200. Hence, it is not possible to sufficiently reduce the current of the resistor string 200 unless a threshold voltage of the transistor is sufficiently small. It is easily understood that when a precharge/predischarge circuit is provided for making high-speed driving to around a level voltage by precharging and predischarging, it is possible to sufficiently reduce the current of the resistor string 200.
Meanwhile, the feedback driving circuit shown in FIGS. 5 and 6 can readily achieve high-speed driving. However, in order to drive the data lines with high voltage accuracy in a stable manner, it is necessary to provide a phase compensation means for preventing oscillation.
In the case where idling current is reduced by the constant current circuit like the operational amplifier of FIG. 5, it is necessary to apply the idling current (static current) which is large enough to rapidly charge and discharge a phase compensating capacity.
Further, in case of the operational amplifier shown in FIG. 5, source voltage is predischarged for each output period. In case of continuous driving at the same level voltage as well, the data lines need to be predischarged for each output period. Thus, excessive charge/discharge power is consumed.
Furthermore, in case of the driving circuit shown in FIG. 6, only one of the charging operation and the discharging operation is carried out in driving data lines during an output period. Hence, in case of the data line having a relatively small capacity, a driving voltage may be largely shifted from a selected level voltage.
Moreover, other than the configurations shown in FIGS. 5 and 6, there is proposed a method of temporarily bringing the operational amplifier to a non-operation state to reduce power consumption caused by idling current in the driving circuit using the operational amplifier. However, an output voltage is unstable until the phase compensating capacity is stable in charging and discharging at the start of the operation of the operational amplifier. When the operational amplifier is frequently switched between an operation and a non-operation, it is difficult to produce an output with high voltage accuracy, and power consumption increases due to charging and discharging of a period having an unstable output.
A first object of the present invention is to provide a driving circuit and so on that achieves a high-speed operation and low power consumption.
A second object of the present invention is to provide a driving circuit and so on that achieves high accuracy of output voltage, a high-speed operation, and low power consumption.
In order to attain the above objects, a first driving circuit of the present invention includes an output circuit for outputting output voltage to a driving output terminal in response to input voltage and a precharge/predischarge circuit for driving the driving output terminal in response to the input voltage, and is characterized in that the precharge/predischarge circuit include:
a first output stage which is controlled by a first operation control signal and includes a first constant current circuit having a discharging function and a charging means;
a second output stage which is controlled by a second operation control signal and includes a second constant current circuit having a charging function and a discharging means; and
at least a single differential circuit which is controlled by a third operation control signal and includes at least a single input terminal for receiving the input voltage and an output terminal connected to the input terminals of the first output stage and the second output stage, and
the output terminals of the first output stage and the second output stage which are connected in common to said driving output terminal.
A second driving circuit of the present invention includes an output circuit for outputting output voltage to a driving output terminal in response to input voltage, a precharge/predischarge circuit for driving the driving output terminal in response to the input voltage, a multilevel voltage generating circuit for generating a plurality of level voltages, and a means for selecting the plurality of level voltages and supplying the voltages as input voltage of the output circuit, and is characterized in that the precharge/predischarge circuit includes:
a first output stage which is controlled by the first operation control signal and includes a first constant current circuit having a discharging function and a charging means;
a second output stage which is controlled by the second operation control signal and includes a second constant current circuit having a charging function and a discharging means; and
at least a single differential circuit which is controlled by a third operation control signal and includes at least a single input terminal for receiving the input voltage and an output terminal connected to the input terminals of the first output stage and the second output stage, and
the output terminals of the first output stage and the second output stage which are connected in common to said driving output terminal.
A third driving circuit of the present invention includes a first output circuit for outputting a first output voltage to a first driving output terminal in response to a first input voltage, a second output circuit for outputting a second output voltage to a second driving output terminal in response to a second input voltage, and a precharge/predischarge circuit for driving the first and second driving output terminals in response to the first and second input voltages, and is characterized in that the precharge/predischarge circuit includes:
a first output stage including a first constant current circuit having a discharging function and a charging means;
a second output stage including a second constant current circuit having a charging function and a discharging means;
a first differential circuit having at least a single input terminal for receiving the first input voltage or the second input voltage and an output terminal connected to the input terminal of the first output stage;
a second differential circuit having at least a single input terminal for receiving the first input voltage or the second input voltage and an output terminal connected to the input terminal of the second output stage; and
the output terminals of the first and second output stages which are connected in common, and connected to the first or second driving output terminals.
a switching group for connecting the first and second output circuits and the first differential circuit and the first output stage or the second differential circuit and the second output stage, and
in an output period when the first and second output circuits and the switch group are controlled and desired voltages are outputted to the first and second driving output terminals, at least the precharge/predischarge circuit is operated in the first half of the output period and only the two output circuits are operated in the second half of the output period.
A fourth driving circuit of the present invention includes an output circuit for inputting an input signal voltage from an input terminal to drive an output terminal, and a precharge/predischarge circuit for precharging/predischarging the output terminal and is characterized in that the precharge/predischarge circuit includes;
first and second differential circuits for differential-inputting an input signal voltage from the input terminal and an output signal voltage of the output terminal;
a first output stage including a first conductive transistor and a first switch connected in series between a high-potential side power source and the output terminal, the first conductive transistor having a control terminal connected to an output voltage of the first differential circuit to be turned on and off, and having when being turned on, a current applied by the output voltage controlled to charge output terminal from a high-potential side power source, and the first switch being subjected to on-off control by an operation control signal, and a first constant current source circuit, which discharges from the output terminal to the low-potential side power source, and a second switch, which is subjected to on-off control by an operation control signal, connected in series between the output terminal and the low-potential side power source; and
a second output stage including a second conductive transistor and a third switch connected in series between a low-potential side power source and the output terminal, the second conductive transistor having a control terminal connected to an output voltage of the second differential circuit to be turned on and off, and having, when being turned on, a current applied by the output voltage is controlled to discharge from the output terminal to the low-potential side power source, and the third switch being subjected to on-off control by an operation control signal, and a second constant current source circuit, which charges the output terminal from the high-potential side power source, and a fourth switch, which is subjected to on-off control by the operation control signal, connected in series between the output terminal and the high-potential side power source.
A fifth driving circuit of the present invention includes an output circuit for inputting an input signal voltage from an input terminal to drive an output terminal, and a precharge/predischarge circuit for precharging and predischarging the output terminal, and is characterized in that the precharge/predischarge circuit includes:
first and second differential circuits for differential-inputting an input signal voltage from the input terminal and an output signal voltage from the output terminal;
a first output stage including a first conductive transistor and a first switch connected in series between a high-potential side power source and the output terminal, the first conductive transistor having a control terminal connected to a first output voltage of the first differential circuit to be turned on and off, and having, when being turned on, a current applied by the first output voltage controlled to charge the output terminal from a high-potential side power source, and the first switch being subjected to on-off control by an operation control signal, and a first constant current source circuit, which discharges from the output terminal to the low-potential side power source, and a second switch, which is subjected to on-off control by the operation control signal, connected in series between the output terminal and the low-potential side power source, and
a second output stage including a second conductive transistor and a third switch connected in series between a low-potential side power source and the output terminal, the second conductive transistor having a control terminal connected to a second output voltage of the second differential circuit to be turned on and off, and having, when being turned on, current applied by the output voltage controlled to discharge from the output terminal to the low-potential side power source, and the third switch being subjected to on-off control by the operation control signal, and a second constant current source circuit, which charges the output terminal from the high-potential side power source, and a fourth switch, which is subjected to on-off control by the operation control signal, connected in series between the output terminal and the high-potential side power source.
The precharge/predischarge circuit of the present invention is characterized by including:
a first output stage which is controlled by a first operation control signal and includes a first constant current circuit having a discharging function and a charging means;
a second output stage which is controlled by a second operation control signal and includes a second constant current circuit having a charging function and a discharging means; and
at least a single differential circuit which is controlled by a third operation control signal and includes a first input terminal, a second input terminal connected to the output terminals of both the first output stage and the second output stage, and an output terminal connected to both the input terminals of the first output stage and the second output stage.
The liquid crystal display device of the present invention is characterized by including the driving circuit or the precharge/predischarge circuit of the present invention.